1. Field of the Invention
The present invention relates to a display device, a method of controlling the display device, and a projection-type display apparatus and, in particular, to a display device which concurrently writes a video signal on a plurality of pixels at a time in a horizontal direction on a display having a matrix of pixels, a method of controlling the display device, and a projection-type display apparatus incorporating the display device.
2. Description of the Related Art
Liquid-crystal display (LCD) devices employing pixels as a display element typically use a digital signal processor IC that is manufactured using a MOS process of a gate array. After being subjected to a predetermined signal process of the digital signal processor IC, digital data is digital-to-analog converted by a digital-to-analog (D/A) converter. The resulting analog signal is then supplied to a liquid-crystal display (LCD) panel through an LCD driver. The LCD panel includes a matrix of pixels, each including a liquid crystal cell.
Since a write speed of the LCD panel is not high enough to successively write an input video signal on the dots (pixels) one by one, the video signal is typically written onto a plurality of pixels in a horizontal direction of the display at a time. In such a liquid-crystal display device of multi-pixel simultaneous writing, a sequentially and successively input video signal must be converted into a parallel signals to be written on a plurality of pixels at a time.
For example, in a liquid-crystal display device that writes the video signal on six horizontal pixels at a time, a sequentially input video signal is converted to six parallel video signals for the six respective pixels having the same timing. The six parallel video signals are then concurrently written onto six signal lines within a duration of time for the six pixels. This parallel processing is performed by an LCD driver when the video signal is subjected to a sample-and-hold process.
A sample-and-hold pulse for use in the parallel processing is generated as a timing signal in synchronization with a horizontal synchronization signal. The signal lines for conducting six-parallel video signal are physically connected to the LCD panel. A start position of the video is uniquely determined by the timing signals and a display start timing signal to the LCD panel.
The LCD panel includes signal line selection switches to select six signal lines at a time. The signal line selection switch selects six signal lines at a time to simultaneously write the video signal on the six pixels at a time. The signal line selection switches are selected in response to a switch pulse (a writing signal) successively generated in synchronization with the video signal. When the signal line selection switches are successively selected, the video signal is simultaneously conducted to the six signal lines through the selected signal selection switch.
The switch pulses and the video signal are distorted by the effect of resistances and capacitances of the signal lines that conduct these signals. An optimum display cannot be obtained without adjusting the phase relationship between the switch pulses and the video signal. An inappropriate phase relationship between the switch pulses and the video signal may leak the video signal to a location ahead of or behind the right position thereof by six pixels, thereby presenting double pictures. For example, if the phase relationship is destroyed when a single vertical line is displayed, the signal vertical line may appear on a location ahead of or behind the right location by six pixels.
Japanese Unexamined Patent Application Publication No. 2002-108299 discloses a technique which adjusts the phase relationship between a timing signal for simultaneously writing a video signal, namely, a switch pulse (writing signal) and the video signal with a precision of at least dot clock frequency without changing the center position of an image. In accordance with this conventional art, a timing generator adjusts the phase of the pulse signal serving as a reference for use in the generation of the switch pulse so that the phase relationship between the video signal and the switch pulse is adjusted without changing the center position of the image with a precision of at least the dot clock frequency.
The conventional art is effective for adjusting the phase relationship between the writing signal for simultaneously writing the video signal and the video signal on a liquid-crystal display device prior to a shipment thereof, but is ineffective for adjusting the phase relationship subsequent to the shipment. Even if an optimum adjustment is achieved prior to the shipment, the phase relationship may be destroyed due to a delay in liquid-crystal driving pulses because circuit elements are subject to temperature cycles and aging after shipment. An optimum image is not achieved.